Inventor, Direct Write Standard Cell Architect

Experience | Masters in EE plus 5 years relevant experience

Attitude | "Impact the world"

Location | Saratoga, CA

Description

The ideal candidate possesses both deep silicon design skills at the layout level, as well as a comprehensive understanding of EDA design flows and software. The interaction between the silicon structure of a cell based architecture (standard cell, structured ASIC, FPGA, or gate array) and software capabilities determines the efficiency and performance of the complete solution. The candidate will have experience in the trade off analysis necessary for standard cell architecture evaluation. This includes reasoning at the layout level about the effects of manufacturability constraints and that impact on the EDA based design flow. The unique opportunity here is in the innovation and definition a new family of standard cell architectures that encompasses new and unique aspects of manufacturability constraints. Additionally, knowledge of the EDA tool chain and the various design kit contents and how to produce them is assumed. This includes library characterization, .lib and lef generation as well as the necessary verification steps.

Please email us if you're interested.

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